Graph Neural Network-Based Fault Localization for Intelligent Hardware Verification in Large-Scale Circuit Designs
Keywords:
Graph neural networks; fault localization; hardware verification; electronic design automation; large-scale circuits; intelligent verification; socio-technical infrastructure; graph partitioning; model checking; robustnessAbstract
Large-scale circuit verification has become a critical bottleneck in modern hardware development because design complexity, integration density, and heterogeneous intellectual property increase the difficulty of locating faults across deeply interconnected structures. This paper examines graph neural network-based fault localization as a system-level capability for intelligent hardware verification. The analysis treats circuits as relational graphs whose components, interconnects, and verification artifacts carry heterogeneous semantic information. Graph neural networks can aggregate local structural evidence and propagate diagnostic signals across neighborhoods, enabling fault localization to move beyond isolated rule-based analysis toward context-sensitive reasoning. The paper develops an architectural account of such systems, including graph construction, partitioning, feature governance, model deployment, human-in-the-loop verification, and infrastructure requirements. It also examines structural trade-offs among accuracy, explainability, latency, scalability, and sustainability. Particular attention is given to robustness under noisy verification traces, fairness in accessibility to verification intelligence, governance of automated diagnostic authority, and policy implications for safety-critical hardware domains. Case illustrations compare graph-based fault localization with conventional model checking, equivalence checking, and logic synthesis diagnostics. The conclusion argues that graph neural network fault localization is most credible when embedded within a socio-technical verification infrastructure that preserves human accountability, sustains data quality, and aligns model behavior with engineering and regulatory expectations.
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This article is published under the Creative Commons Attribution 4.0 International License (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
